EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 174

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
PWM0 Signal
PWM0 Signal
PWM Nonoverlapping Output Pair Delays
Figure 32. PWM AND/OR Gating Functional Diagram
If the user enables the OR function on all PWM outputs and PADR0 is set to 1,
then the PWM0 output on PA0 is forced High. Similarly, if the user selects the
AND function on all PWM outputs and PADR0 is set to a 0, then the PWM0 output
on PA0 is forced Low.
A delay can be added between the falling edge of the PWM (PWM) outputs and
the rising edge of the PWM (PWM) outputs. This delay can be set to assure that
even with load and output drive variations there will be no overlap between the
falling edge of a PWM (PWM) output and the rising edge of its paired output. The
selected delay is global to all four PWM pairs. The delay duration is software-
selectable using the 4-bit field TMR3_PWM_CTL2[PWM_DLY]. The duration is
programmable in units of the system clock (SCLK), from 0 SCLK periods to 15
SCLK periods. The TMR3_PWM_CTL2[PWM_DLY] bits are mapped directly to a
PADR0
PADR4
P R E L I M I N A R Y
TMR3_PWM_CTL2[5:4]
TMR3_PWM_CTL2[7:6]
00
01
10
11
00
01
10
11
2
2
Programmable Reload Timers
Product Specification
PA0
PA4
eZ80F91 MCU
PWM0 Output
PWM0 Output
155