EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 95

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
I/O Chip Select Operation
Wait States
I/O Chip Selects can only be active when the CPU is performing I/O instructions.
Because the I/O space is separate from the memory space in the eZ80F91
device, there can never be a conflict between I/O and memory addresses.
The eZ80F91 supports a 16-bit I/O address. The I/O Chip Select logic decodes
the High byte of the I/O address, ADDR[15:8]. Because the upper byte of the
address bus, ADDR[23:16], is ignored, the I/O devices can always be accessed
from within either memory mode (ADL or Z80). The MBASE offset value used for
setting the Z80 MEMORY mode page is also always ignored.
Four I/O Chip Selects are available with the eZ80F91 device. To generate a par-
ticular I/O Chip Select, the following conditions must be met:
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If all of the foregoing conditions are met to generate an I/O Chip Select, then the
following actions occur:
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For each of the Chip Selects, programmable wait states can be asserted to pro-
vide external devices with additional clock cycles to complete their Read or Write
operations. The number of wait states for a particular Chip Select is controlled by
the 3-bit field CSx_WAIT (CSx_CTL[7:5]). The wait states can be independently
programmed to provide 0 to 7 wait states for each Chip Select. The wait states
idle the CPU for the specified number of system clock cycles.
The Chip Select is enabled by setting CSx_EN to 1
The Chip Select is configured for I/O by setting CSX_IO to 1
An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0]
No higher-priority (lower-number) Chip Select meets the above conditions
The I/O address is not within the on-chip peripheral address range
00FFh
0080h ADDR[15:0]
An I/O instruction must be executing
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven
Low)
IORQ is asserted (driven Low)
Depending upon the instruction, either RD or WR is asserted (driven Low)
. On-chip peripheral registers assume priority for all addresses where:
00FFh
P R E L I M I N A R Y
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
0080h–
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