EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 97

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
Figure 8. Example: Wait State Read Operation
PS019209-0504
ADDR[23:0]
DATA[7:0]
Chip Selects During Bus Request/Bus Acknowledge Cycles
Bus Mode Controller
INSTRD
(output)
MREQ
SCLK
CSx
RD
When the CPU relinquishes the address bus to an external peripheral in response
to an external bus request (BUSREQ), it drives the bus acknowledge pin
(BUSACK) Low. The external peripheral can then drive the address bus (and data
bus). The CPU continues to generate Chip Select signals in response to the
address on the bus. External devices cannot access the internal registers of the
eZ80F91.
The bus mode controller allows the address and data bus timing and signal for-
mats of the eZ80F91 to be configured to connect seamlessly with external
eZ80
the chip selects can be configured independently using the Chip Select Bus Mode
®
-, Z80™-, Intel™-, or Motorola-compatible devices. Bus modes for each of
T
CLK
P R E L I M I N A R Y
T
WAIT
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
78

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