EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 173

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
AND/OR Gating of the PWM Outputs
Note:
Under certain circumstances, electric motors driven by the PWM logic can
encounter rough operation. In essence, cycles can be skipped if the PWM wave-
form edge is not carefully modified.
Without special consideration, if a PWM generator looks for a particular count to
make a state transition, and if the edge transition value changes to a value that
already occurred in the current counter count-down cycle, then the transition is
missed. The PWM generator holds the current output state until the counter
reloads and cycles through to the appropriate edge transition value again. In
effect, an entire cycle of the PWM waveform can be skipped with the signal held
at a DC value. The change in PWM waveform duty cycle from cycle to cycle must
be limited to some fraction of a period to avoid rough running. To avoid uninten-
tional roughness due to timing of the load operation for the register values in
question, the PWM edge transition values are double-buffered and exhibit the fol-
lowing behavior:
1. When the PWM generators are disabled, PWM edge transition values written
2. When the PWM generators are enabled, a PWM edge transition value is
When in Multi-PWM mode, it is possible for the user to turn off PWM propagation
to the pins without disabling the PWM generator. This feature is global and applies
to all enabled PWM generators. The function is implemented by applying digital
logic (AND or OR functions) to combine the corresponding bits in the port output
register with the PWM and PWM outputs.
The AND or OR functions are enabled on all PWM outputs by setting
TMR3_PWM_CTL2[AO_EN] to either a 01b (AND) or 10b (OR). Any other value
disables this feature. Likewise, the AND or OR functions are enabled on all PWM
outputs by setting TMR3_PWM_CTL2[AON_EN] to either a 01b (AND) or 10b
(OR). Any other value disables this feature. A functional block diagram for the
AND/OR gating feature for PWM0 and PWM0 is illustrated in Figure 32. The func-
tionality for the other three PWM pairs is identical.
by the CPU are immediately loaded into the PWM edge transition registers.
loaded into a buffer register and transferred to its destination register only
upon a specific transition event. A rising edge transition value is only loaded
upon a falling edge transition event, and a falling edge transition value is only
loaded upon a rising edge transition event.
P R E L I M I N A R Y
Programmable Reload Timers
Product Specification
eZ80F91 MCU
154