EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 253

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
I
The I2C_CTL register is a control register that is used to control the interrupts and
the master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when
the IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains
Low.
When the Bus Enable bit (ENAB) is set to 0, the I
are ignored and the I
When ENAB is set to 1, the I
general call address if the GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I
and sends a START condition on the bus when the bus is free. If the STA bit is set
to 1 when the I
transmitted, then a repeated START condition is sent. If the STA bit is set to 1
when the I
transfer in SLAVE mode and then enters MASTER mode when the bus is
released. The STA bit is automatically cleared after a START condition is set.
Writing a 0 to the STA bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition
is transmitted on the I
ule operates as if a STOP condition is received, but no STOP condition is trans-
mitted. If both STA and STP bits are set, the I
condition (if in MASTER mode), then transmits the START condition. The STP bit
is cleared to 0 automatically. Writing a 0 to this bit produces no effect.
The I
ble 31 I
F8h
IFLG is set by the I
data transfer is suspended. When a 0 is written to IFLG, the interrupt is cleared
and the I
When the I
the acknowledge clock pulse on the I
•
•
•
2
C Control Register
. If IFLG is set to 1 and the IEN bit is also set, an interrupt is generated. When
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit
slave address is received
The general call address is received and the General Call Enable bit in
I2C_SAR is set to 1
A data byte is received while in MASTER or SLAVE modes
2
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possi-
2
C states is entered. The only state that does not set the IFLG bit is state
2
C clock line is released.
2
2
C block is being accessed in SLAVE mode, the I
C Acknowledge bit (AAK) is set to 1, an acknowledge is sent during
2
C module is already in MASTER mode and one or more bytes are
2
C, the Low period of the I
2
2
C module does not respond to any address on the bus.
C bus. If the STP bit is set to 1 in slave move, the I
P R E L I M I N A R Y
2
C responds to calls to its slave address and to the
2
C bus if:
2
C bus.
2
2
C bus clock line is stretched and the
C block first transmits the STOP
2
C bus inputs SCLx and SDAx
2
C enters MASTER mode
Product Specification
2
C completes the data
I
2
C Serial I/O Interface
eZ80F91 MCU
2
C mod-
234