EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 279

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 147. EMAC Interpacket Gap Register
(EMAC_IPGT = 002Dh)
EMAC Non-Back-To-Back IPG Register—Part 1
Part 1 of the EMAC Non-Back-To-Back IPG Register is a programmable field rep-
resenting the optional carrier sense window referenced in IEEE 802.3/4.2.3.2.1
Carrier Deference. If a carrier is detected during the timing of IPGR1, the EMAC
defers to the carrier. If, however, the carrier becomes active after IPGR1, the
EMAC continues timing for IPGR2 and transmits, knowingly causing a collision.
This collision acts to ensure fair access to the medium. Its range of values is
to IPGR2. See Table 148. The default setting of 0Ch represents the Carrier Sense
Window Referencing depicted tin IEEE 802.3, Section 4.2.3.2.1.
Table 148. EMAC Non-Back-To-Back IPG Register—Part 1
(EMAC_IPGR1 = 002Eh)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write
Bit
Position
7
[6:0]
IPGT
Bit
Reset
CPU Access
Note: R/W = Read/Write
Bit
Position
7
[6:0]
IPGR 1
Value
0
00h–
7Fh
Value
0
00h–
7Fh
Description
Reserved.
The number of octets of IPG.
R/W
Description
Reserved.
This is a programmable field representing the optional carrier
sense window referenced in IEEE 802.3/4.2.3.2.1 Carrier
Deference.
R
P R E L I M I N A R Y
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
1
4
0
R/W
R/W
Ethernet Media Access Controller
3
0
3
1
Product Specification
R/W
R/W
2
1
2
1
eZ80F91 MCU
R/W
R/W
1
0
1
0
R/W
R/W
00h
0
1
0
0
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