EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 210
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 210 of 396
- Download datasheet (5Mb)
PS019209-0504
UART Registers
After a system reset, all UART registers are set to their default values. Any Writes
to unused registers or register bits are ignored and reads return a value of 0. For
compatibility with future revisions, unused bits within a register should always be
written with a value of 0. Read/Write attributes, reset conditions, and bit descrip-
tions of all of the UART registers are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte
written to this register are selected for transmission. The Transmit FIFO is
mapped at this address. The user can write up to 16 bytes for transmission at one
time to this address if the FIFO is enabled by the application. If the FIFO is dis-
abled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and
UARTx_BRG_L registers. See Table 96.
Table 96. UART Transmit Holding Registers
(UART0_THR = 00C0h, UART1_THR = 00D0h)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
T
x
D
Value
00h–
FFh
Description
Transmit data byte.
W
P R E L I M I N A R Y
X
7
W
6
X
W
X
5
Universal Asynchronous Receiver/Transmitter
W
X
4
W
X
3
Product Specification
W
X
2
eZ80F91 MCU
W
X
1
W
X
0
191
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