EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 342

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Power Requirement to the Phase-Locked Loop Function
PLL Registers
Figure 61. Normal PLL Programming Flow
Regardless of whether or not the developer chooses to use the PLL module block
as a clock source for the eZ80F91 device, the PLL_V
nected to a V
supply for proper operation of the eZ80F91 using any system clock source.
PLL Divider Control Register—Low and High Bytes
This register is designed such that the 11-bit divider value is loaded into the
divider module whenever the PLL_DIV_H register is written. Therefore, the proce-
dure should be to load the PLL_DIV_L register, followed by the PLL_DIV_H regis-
ter, for the divider to receive the appropriate value.
Set SCLK MUX to PLL (PLL_CTL0)
{Charge Pump & Lock criteria}
PLL_DIV_L then PLL_DIV_H
Disable Lock Interrupt Mask
Execute Application Code
Execute instructions with
SCLK = XTAL Oscillator
Upon Lock Interrupt:
{Interrupts & PLL}
POR/System
{PLL Divider}
(PLL_CTL1)
PLL_CTL0
PLL_CTL1
DD
Program:
Enable:
Reset
supply and the PLL_V
P R E L I M I N A R Y
SS
(pin 84) must be connected to a V
DD
(pin 87) must be con-
Product Specification
Phase-Locked Loop
eZ80F91 MCU
SS
323