EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 280

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Note:
EMAC Non-Back-To-Back IPG Register—Part 2
Part 2 of the EMAC Non-Back-To-Back IPG Register is a programmable field rep-
resenting the non-back-to-back interpacket gap. Its default is
sents the minimum IPG of 0.96 µs at 100 Mbps or 9.6 µs at 10 Mbps. See Table
149.
Table 149. EMAC Non-Back-To-Back IPG Register—Part 2
(EMAC_IPGR2 = 002Fh)
EMAC Maximum Frame Length Register—Low and High Bytes
The 16-bit field resets to
1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is more appropriate, program this field. See Tables 150 and 151.
If a proprietary header is allowed, this field should be adjusted accordingly. For
example, if 12-byte headers are prepended to frames, MAXF should be set to
1524 octets to allow the maximum VLAN tagged frame plus the 12-byte header.
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write
Bit
Position
7
[6:0]
IPGR2
Value
0
00h–
7Fh
Description
Reserved.
This is a programmable field representing the non-back-to-
back interpacket gap.
0600h
P R E L I M I N A R Y
R
7
0
, which represents a maximum Receive frame of
R/W
6
0
R/W
5
0
R/W
4
1
R/W
Ethernet Media Access Controller
3
0
Product Specification
R/W
12h
2
0
, which repre-
eZ80F91 MCU
R/W
1
1
R/W
0
0
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