EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 117

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Bus Arbiter
PS019209-0504
The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of
the CPU memory interface bus. During normal operation, the eZ80F91 device is
the bus master. External devices can request master use of the bus by asserting
the BUSREQ pin. The Bus Arbiter forces the CPU to release the bus after com-
pleting the current instruction. When the CPU releases the bus, the Bus Arbiter
asserts the BUSACK pin to notify the external device that it can master the bus.
When an external device assumes control of the memory interface bus, the bus
acknowledge cycle is complete. Table 30 shows the status of the pins on the
eZ80F91 device during bus acknowledge cycles.
During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device
can be used by an external bus master to control the memory and I/O Chip
Selects.
Table 30. eZ80F91
Pin Symbol
ADDR23..ADDR0
CS0
CS1
CS2
CS3
DATA7..0
IORQ
MREQ
RD
WR
INSTRD
Pin Status During Bus Acknowledge Cycles
Signal Direction
Input
Output
Output
Output
Output
Tristate
Input
Input
Tristate
Tristate
Tristate
P R E L I M I N A R Y
Description
Allows external bus master to utilize the
Chip Select logic of the eZ80F91.
Normal operation.
Normal operation.
Normal operation.
Normal operation.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to utilize the
Chip Select logic of the eZ80F91.
Allows external bus master to utilize the
Chip Select logic of the eZ80F91.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to communicate
with external peripherals.
Allows external bus master to communicate
with external peripherals.
Product Specification
eZ80F91 MCU
Bus Arbiter
98