EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 76

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
Table 5. Clock Peripheral Power-Down Register 2
(CLK_PPD2 = 00DCh)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
PHI_OFF
[6:4]
3
TIMER3_OFF
2
TIMER2_OFF
1
TIMER1_OFF
0
TIMER0_OFF
Value Description
1
0
000
1
0
1
0
1
0
1
0
R/W
PHI Clock output is disabled (output is high-impedance).
PHI Clock output is enabled.
Reserved.
System clock to TIMER3 is powered down.
System clock to TIMER3 is powered up.
System clock to TIMER2 is powered down.
System clock to TIMER2 is powered up.
System clock to TIMER1 is powered down.
System clock to TIMER1 is powered up.
System clock to TIMER0 is powered down.
System clock to TIMER0 is powered up.
P R E L I M I N A R Y
7
0
R
6
0
R
5
0
R
4
0
R/W
3
0
Product Specification
R/W
2
0
Low Power Modes
eZ80F91 MCU
R/W
1
0
R/W
0
0
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