EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 246

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 120. I
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit
in the I2C_CTL register. The I
bit and returns to an idle state.
Master Receive
In MASTER RECEIVE mode, the I
transmitter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
is loaded into the I2C_SR register. The I2C_DR register should be loaded with the
slave address (or the first part of a 10-bit slave address), with the lsb set to 1 to
signify a Read. The IFLG bit should be cleared to 0 as a prompt for the transfer to
continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read
bit are transmitted, the IFLG bit is set and one of the status codes listed in Table
121 is loaded into the I2C_SR register.
Code
28h
30h
38h
I
Data byte transmitted,
ACK received
Data byte transmitted,
ACK not received
Arbitration lost
2
2
C Master Transmit Status Codes For Data Bytes
C State
P R E L I M I N A R Y
2
C then transmits a STOP condition, clears the STP
Microcontroller Response
Write byte to data,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
2
C receives a number of bytes from a slave
Product Specification
Next I
Transmit data byte,
receive ACK.
Transmit repeated
START.
Transmit STOP.
Transmit START
then STOP.
Same as code 28h.
Return to idle.
Transmit START
when bus free.
I
2
C Serial I/O Interface
eZ80F91 MCU
2
C Action
08h
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