EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 254

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
When AAK is cleared to 0, a NACK is sent when a data byte is received in MAS-
TER or SLAVE mode. If AAK is cleared to 0 in SLAVE TRANSMIT mode, the byte
in the I2C_DR register is assumed to be the final byte. After this byte is transmit-
ted, the I
ule does not respond to its slave address unless AAK is set to 1. See Table 127.
Table 127. I
(I2C_CTL = 00CBh)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
IEN
6
ENAB
5
STA
4
STP
3
IFLG
2
AAK
[1:0]
2
C block enters the
2
C Control Register
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
00
R/W
I
I
The I
ignored.
The I
Master mode START condition is sent.
Master mode start-transmit START condition on the bus.
Master mode STOP condition is sent.
Master mode stop-transmit STOP condition on the bus.
I
I
Not Acknowledge.
Acknowledge.
Reserved.
P R E L I M I N A R Y
7
0
2
2
2
2
C interrupt is disabled.
C interrupt is enabled.
C interrupt flag is not set.
C interrupt flag is set.
C8h
2
2
C bus (SCL/SDA) is disabled and all inputs are
C bus (SCL/SDA) is enabled.
R/W
6
0
state, then returns to an idle state. The I
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
I
2
C Serial I/O Interface
eZ80F91 MCU
R
1
0
2
C mod-
R
0
0
235