EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 321

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 192. ZDI Read/Write Control Register Functions*
(ZDI_RW_CTL = 16h in the ZDI Register Write Only Address Space) (Continued)
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It
enables or disables bus acknowledge in ZDI DEBUG mode and allows ZDI to
force assertion of the BUSACK signal. This register should only be written during
ZDI Debug mode (that is, following a break). See Table 193.
Table 193. ZDI Bus Control Register
(ZDI_BUS_CTL = 17h in the ZDI Register Write Only Address Space)
Hex
Value
09
0A
0B
Note: *The CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly. The ZDI
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
ZDI_BUSAK_EN
programmer must execute the exchange instruction (EXX) to gain access to the alternate
CPU register set.
Command
Reset ADL
ADL
Exchange CPU register sets
AF
BC
DE
HL
Read memory from current
PC value, increment PC
AF’
HL’
Value
0
1
BC’
DE’
0
W
P R E L I M I N A R Y
7
0
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK,
is not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
W
6
0
W
5
0
Hex
Value
89
8A
8B
W
4
0
Command
Reserved
Reserved
Write memory from current PC
value, increment PC
W
3
0
Product Specification
W
ZiLOG Debug Interface
2
0
eZ80F91 MCU
W
1
0
W
0
0
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