EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 114

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
Chip Select x Control Register
The Chip Select x Control register, detailed in Table 28, enables the Chip Selects,
specifies the type of Chip Select, and sets the number of wait states. The reset
state for the Chip Select 0 Control register is
other Chip Select control registers is
Table 28. Chip Select x Control Register
(CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSX_WAIT
4
CSX_IO
3
CSX_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
R/W
0 wait states are asserted when this Chip Select is active.
1 wait state is asserted when this Chip Select is active.
2 wait states are asserted when this Chip Select is active.
3 wait states are asserted when this Chip Select is active.
4 wait states are asserted when this Chip Select is active.
5 wait states are asserted when this Chip Select is active.
6 wait states are asserted when this Chip Select is active.
7 wait states are asserted when this Chip Select is active.
Chip Select is configured as a Memory Chip Select.
Chip Select is configured as an I/O Chip Select.
Chip Select is disabled.
Chip Select is enabled.
Reserved.
P R E L I M I N A R Y
7
1
0
0
0
R/W
6
1
0
0
0
00h
R/W
5
1
0
0
0
.
E8h
R/W
4
0
0
0
0
, while the reset state for the 3
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
R
2
0
0
0
0
eZ80F91 MCU
R
1
0
0
0
0
R
0
0
0
0
0
95

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