EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 113

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Chip Select x Upper Bound Register
For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in
Table 27, defines the upper bound of the address range for which the correspond-
ing Chip Select (if enabled) can be active. For I/O Chip Selects, this register pro-
duces no effect. The reset state for the Chip Select 0 Upper Bound register is
while the reset state for the other Chip Select upper bound registers is
Table 27. Chip Select x Upper Bound Register
(CS0_UBR = 00A9h, CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h)
Bit
CS0_UBR Reset
CS1_UBR Reset
CS2_UBR Reset
CS3_UBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_UBR
Value Description
00h–
FFh
R/W
For Memory Chip Selects (
This byte specifies the upper bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in these
registers for determining whether a Chip Select signal should
be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
P R E L I M I N A R Y
7
1
0
0
0
R/W
6
1
0
0
0
R/W
5
1
0
0
0
R/W
4
1
0
0
0
CSX_IO
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
= 0)
R/W
2
1
0
0
0
eZ80F91 MCU
R/W
1
1
0
0
0
00h
.
R/W
FFh
0
1
0
0
0
,
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