EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 277

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 145. EMAC_IPGT Back-to-Back Settings for Full/Half Duplex Modes*
PS019209-0504
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
Duplex
Half
12h
Clock Period = 40 nsec
MII, RMII/SMII, PMD
EMAC Interpacket Gap
(100 Mbps)
Duplex
IPGT[6:0]
Full
0Dh
0Ch
0Bh
10h
15h
20h
EMAC Interpacket Gap Overview
Interpacket gap (IPG) is measured between the last nibble of the frame check
sequence (FCS) and the first nibble of the preamble of the next packet. Three reg-
isters are available to fine tune the IPG, the EMAC_IPGT, EMAC_IPGR1, and the
EMAC_IPGR2. The first register EMAC_IPGT determines the back-to-back
Transmit IPG. The other two registers determine the non-back-to-back IPG in two
parts. Table 145 shows the values for the EMAC_IPGT and the corresponding
IPGs for both full-duplex and half-duplex modes.
The equations for back-to-back Transmit IPG are determined by the following:
Table 146 shows the IPGR2 settings for the non-back-to-back packets.
Full Duplex Mode (3 clocks + IPGT clocks) * clock period = IPG
Half Duplex Mode (6 clocks + IPGT clocks) * clock period = IPG
Interpacket
0.12 µs
0.44 µs
0.60 µs
0.76 µs
0.96 µs
1.40 µs
Gap
Duplex
Half
12h
Clock Period = 400 nsec
P R E L I M I N A R Y
MII, RMII/SMII
Duplex
(10 Mbps)
IPGT[6:0]
Full
0Ch
00h
08h
10h
15h
20h
Interpacket
14.0 µs
1.2 µs
4.4 µs
6.0 µs
7.5 µs
9.6 µs
Gap
Duplex
Half
5Ah
Ethernet Media Access Controller
Clock Period = 100 nsec
Product Specification
ENDEC Mode
Duplex
(10 Mbps)
IPGT[6:0]
Full
5Dh
10h
18h
20h
40h
20h
eZ80F91 MCU
Interpacket
13.0 µs
1.9 µs
2.7 µs
3.5 µs
6.7 µs
9.6 µs
Gap
258