EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 301

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
EMAC Transmit Read Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Transmit Read Pointer Register are always zero. See Table 179.
Table 179. EMAC Transmit Read Pointer Register—High Byte
(EMAC_TRP_H = 0054h)
EMAC Receive Blocks Left Register—Low and High Bytes
This register reports the number of buffers left in the Receive EMAC shared mem-
ory. The hardware uses this information, along with the Block-Level set in the
EMAC_BUFSZ register, to determine when to transmit a pause control frame.
Software can use this information to determine when it should request that a
pause control frame be transmitted (by setting bit 6 of the EMAC_CFG4 register).
For the BlksLeft logic to operate properly, the Receive buffer must contain at least
one more packet buffer than the number of packet buffers required for the largest
packet. That is, one packet cannot fill the entire Receive buffer. Otherwise, the
BlksLeft will be in error. See Tables 180 and 181.
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_TRP_H
Value
00h–
1Fh
RO
P R E L I M I N A R Y
7
0
Description
These bits represent the High byte of the 2-byte EMAC
TxDMA
EMAC_TRP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit
0 is bit 8 of the 16-bit value.
RO
6
0
Transmit Read Pointer
RO
5
0
RO
4
0
Ethernet Media Access Controller
RO
3
0
value, {EMAC_TRP_H,
Product Specification
RO
2
0
eZ80F91 MCU
RO
1
0
RO
0
0
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