EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 278

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 146. EMAC_IPGT Non-Back-to-Back Settings for Full/Half Duplex Modes*
A non-back-to-back Transmit IPG is determined by the following formula:
The difference in values between Tables 145 and 146 is due to the asynchronous
nature of the Carrier Sense (CRS). The CRS must undergo a 2-clock synchroni-
zation before the internal Tx state machine can detect it. This synchronization
equates to a 6-clock intrinsic delay between packets instead of the 3-clock intrin-
sic delay in the back-to-back packet mode. More information covering this topic
can be found in the IEEE 802.3/4.2.3.2.1 Carrier Deference section.
EMAC Interpacket Gap Register
The EMAC Interpacket Gap is a programmable field representing the interpacket
gap (IPG) between back-to-back packets. It is the IPG parameter used in full-
duplex and half-duplex modes between back-to-back packets. Set this field to the
appropriate number of IPG octets. The default setting of
mum IPG of 0.96 µs (at 100 Mbps) or 9.6 s (at 10Mbps). See Table 147.
Note: *The IEEE 802.3, 802.3(u) minimum values are shaded.
IPGR2[6:0]
Clock Period = 40 nsec
MII, RMII/SMII, PMD
00h
10h
12h
20h
40h
7Fh
(100 Mbps)
Interpacket
(6 clocks + IPGR2 clocks) * clock period = IPG
0.24 µs
0.88 µs
0.96 µs
1.52 µs
2.80 µs
5.32 µs
Gap
P R E L I M I N A R Y
Clock Period = 400 nsec
IPGR2[6:0]
00h
10h
12h
20h
40h
7Fh
MII, RMII/SMII
(10 Mbps)
Interpacket
15.2 µs
28.0 µs
53.2 µs
2.4 µs
8.8 µs
9.6 µs
Gap
Ethernet Media Access Controller
IPGR2[6:0]
Clock Period = 100 nsec
15h
Product Specification
5Ah
7Fh
00h
10h
20h
40h
represents the mini-
ENDEC Mode
(10 Mbps)
eZ80F91 MCU
Interpacket
13.3 µs
0.6 µs
2.2 µs
3.8 µs
7.0 µs
9.6 µs
Gap
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