EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 297

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
PS019209-0504
EMAC PHY Read Status Data Register—Low and High Bytes
The PHY MII Management Data Register is where the data Read from the PHY is
stored. See Tables 173 and 174.
Table 173. EMAC PHY Read Status Data Register—Low Byte
(EMAC_PRSD_L = 004Eh)
Bit
Position
1
Tx_CF_STAT
0
Tx_DONE_STAT
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_PRSD_L
Value
00h–
FFh
Value
1
0
1
0
P R E L I M I N A R Y
R
7
0
Description
These bits represent the Low byte of the 2-byte EMAC
PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is
bit 0 (lsb) of the 16-bit value.
Description
Transmit Control Frame Interrupt (Transmit Interrupt)
occurs.
Transmit Control Frame Interrupt (Transmit Interrupt)
does not occur.
Transmit Done interrupt (Transmit Interrupt) occurs.
Transmit Done interrupt (Transmit Interrupt) does not
occur.
R
6
0
R
5
0
R
4
0
Ethernet Media Access Controller
R
3
0
Product Specification
R
2
0
eZ80F91 MCU
R
1
0
R
0
0
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