EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 249

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Note:
Note:
When I
F7h
received after a restart. An interrupt is generated and IFLG is set to 1; however,
the status does not change. No second address byte is sent by the master. It is up
to the slave to remember it had been selected prior to the restart.
I
lost during the transmission of an address, and the slave address and Read bit
are received. This action is represented by the status code
ister.
The data byte to be transmitted is loaded into the
is cleared to 0. After the I
is set to 1 and the
mitted is loaded into the
cleared to 0. After the final byte is transmitted, the IFLG is set and the
ister contains
1 before reentering SLAVE mode.
If no ACK is received after transmitting a byte, the IFLG is set and the
ister contains
If a STOP condition is detected after an ACK bit, the I
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master
transmitter.
The I
and a Write bit (lsb = 0) after a START condition. The I
sets the IFLG bit in the
tus code
general call address
code is then
When the I
I2C_SAR
received but no interrupt is generated. IFLG is not set and the status does not
change. The I
received. The I
I
during the transmission of an address, and the slave address and Write bit (or the
general call address if the CGE bit in the
received. The status code in the
2
2
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost
in the I2C_SAR register), it transmits an ACK when the first address byte is
2
C enters SLAVE RECEIVE mode when it receives its own slave address
2
C contains a 10-bit slave address (signified by the address range
60h
register), it transmits an acknowledge after the first address byte is
2
C contains a 10-bit slave address (signified by
70h
. The I
2
C8h
C0h
C generates an interrupt only after the second address byte is
2
C sets the IFLG bit and loads the status code as described above.
.
. The I
and the I
I2C_SR
2
C also enters SLAVE RECEIVE mode when it receives the
00h
I2C_CTL
2
I2C_DR
C then returns to an idle state.
(if the GCE bit in the
2
P R E L I M I N A R Y
C transmits the byte and receives an ACK, the IFLG bit
register contains
2
C returns to an idle state. The AAK bit must be set to
register and the
register, the AAK bit is cleared when the IFLG is
I2C_SR
register is
I2C_SAR
B8h
I2C_SAR
. When the final byte to be trans-
I2C_SR
I2C_DR
register is set to 1) are
68h
2
2
C returns to an idle state.
C transmits an ACK bit and
register is set). The status
if the slave address is
register contains the sta-
register and the IFLG bit
Product Specification
F0h–F7h
B0h
I
in the
2
C Serial I/O Interface
eZ80F91 MCU
in the
I2C_SR
I2C_SR
I2C_SR
F0h–
reg-
reg-
reg-
230