EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 262

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

eZ80F91 MCU
Product Specification
243
the packet from descriptor table bytes 3 and 4. The TxDMA moves the data into
the TxFIFO until the packet length counter downcounts to zero. The TxDMA then
waits for Transmission Complete signal to be asserted to indicate that the packet
is sent and that the Transmit status from the EMAC is valid. The TxDMA updates
the descriptor table status and resets the ownership semaphore, bit 15. Finally,
the Tx_DONE_STAT bit of the
EMAC Interrupt Status Register
is set to 1, the
address field, DMA_Address, is updated from the descriptor table next pointer, NP
(see
Figure
50). The High byte of the status is read to determine if the next packet
is ready to be transmitted.
While the TxDMA is filling the TxFIFO, it monitors two signals from the Transmit
FIFO State Machine (TxFifoSM) to detect error conditions and to determine if the
packet is to be retransmitted (TxDMA_Retry asserted) or the packet is aborted
(TxDMA_Abort asserted). If the packet is aborted, the TxDMA updates the
descriptor status and moves to the next packet. If the packet is to be retried, the
DMA_Address is reset to the start of the packet, the packet length counter is
reloaded from the descriptor table, bytes 3 and 4, and the packet is moved into
the TxFIFO again. When an abort or retry event occurs, the TxDMA asserts the
appropriate signal to reset the TxFIFO Read and Write pointers which clears out
any data that is in the FIFO. The TxFifoSM negates the TxDMA_Abort and/or
TxDMA_Retry signal(s) when the TxFCWP signal is High. This handshaking
maintains synchronization between the TxDMA and the TxFifoSM.
RxDMA
The RxDMA reads the data from the RxFIFO and stores it in the EMAC memory
Receive buffer. When the end of the packet is detected, the RxDMA reads the
next two bytes from the RxFIFO and writes them into the Rx descriptor status LSB
and MSB. The packet length counter is stored into the descriptor table packet
length field, the descriptor table next pointer is written into the Rx descriptor table
and finally the Rx_DONE_STAT bit in the EMAC Interrupt Status Register register
is set to 1.
PS019209-0504
P R E L I M I N A R Y
Ethernet Media Access Controller