EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 93
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
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PS019209-0504
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If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR),
then a particular Chip Select is valid for a single 64 KB page.
Memory Chip Select Priority
A lower-numbered Chip Select is granted priority over a higher-numbered Chip
Select. For example, if the address space of Chip Select 0 overlaps the Chip
Select 1 address space, Chip Select 0 is active. If the address range programmed
for any Chip Select signal overlaps with the address of internal memory, the inter-
nal memory is accorded higher priority. If the particular Chip Select(s) are config-
ured with an address range that overlaps with an internal memory address, then
when the internal memory is accessed, the Chip Select signal is not asserted.
Reset States
On RESET, Chip Select 0 is active for all addresses, because its Lower Bound
register resets to
Chip Select Lower and Upper Bound registers reset to
Memory Chip Select Example
The use of Memory Chip Selects is demonstrated in Figure 6. The associated
control register values are indicated in Table 17. In this example, all 4 Chip
Selects are enabled and configured for memory addresses. Also, CS1 overlaps
with CS0. Because CS0 is prioritized higher than CS1, CS1 is not active for much
of its defined address space.
MREQ is asserted (driven Low)
Depending upon the instruction, either RD or WR is asserted (driven Low)
00h
and its Upper Bound register resets to
P R E L I M I N A R Y
00h
Chip Selects and Wait States
Product Specification
.
FFh
. All of the other
eZ80F91 MCU
74
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