EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 292

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 167. EMAC Receive High Boundary Pointer Register—High Byte
(EMAC_RHBP_H = 0048h)
EMAC Receive Read Pointer Register—Low and High Bytes
The Receive Read Pointer Register should be initialized to the EMAC_BP value
(start of the Receive buffer). This register points to where the next Receive packet
is read from. The EMAC_BP[12:5] is loaded into this register whenever the
EMAC_RST [(HRRFN) is set to 1. The RxDMA block uses the Emac_Rrp[12:5] to
compare to EmacRwp[12:5] for determining how many buffers remain. The result
equates to the EmacBlksLeft register. See Tables 168 and 169.
Table 168. EMAC Receive Read Pointer Register—Low Byte
(EMAC_RRP_L = 0049h)
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RHBP_H
Note: *Bits 7:5 are not used by the EMAC; these bits return 000.
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RRP_L
Value
00h–
FFh
Value
00h–
FFh
R/W
P R E L I M I N A R Y
R
7
1
7
0
Description
These bits represent the High byte of the 2-byte EMAC
Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 15 (msb) of the 16-bit value.
Bit 0 is bit 8 of the 16-bit value.
Description
These bits represent the Low byte of the 2-byte EMAC
Receive Read Pointer value, {EMAC_RRP_H,
EMAC_RRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit
0 (lsb) of the 16-bit value.
R/W
R
6
1
6
0
R/W
R
5
0
5
0
R/W
R
4
0
4
0
R/W
Ethernet Media Access Controller
R
3
0
3
0
Product Specification
R/W
R
2
0
2
0
eZ80F91 MCU
R/W
R
1
0
1
0
R/W
R
0
0
0
0
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