EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 26
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 26 of 396
- Download datasheet (5Mb)
Table 2. Pin Identification on the eZ80F91 Device (Continued)
PS019209-0504
LQFP
Pin #
5
6
7
8
9
10
Note: *PHY represents the physical layer of the OSI model.
BGA
Pin#
D4
C1
C2
E5
D2
D1
Symbol
ADDR4
V
V
ADDR5
ADDR6
ADDR7
DD
SS
Function
Address Bus
Power Supply
Ground
Address Bus
Address Bus
Address Bus
P R E L I M I N A R Y
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Power Supply.
Ground.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Product Specification
Architectural Overview
eZ80F91 MCU
7
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