EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 208

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

eZ80F91 MCU
Product Specification
189
Calculate the UART data rate with the following equation:
System Clock Frequency
UART Data Rate (bits/s)
=
16 X UART Baud Rate Generator Divisor
Upon RESET, the 16-bit BRG divisor value resets to the smallest allowable value
of
. Therefore, the minimum BRG clock divisor ratio is 2. A software Write to
0002h
either the Low- or High-byte registers for the BRG Divisor Latch causes both the
Low and High bytes to load into the BRG counter, and causes the count to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control regis-
ter (UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
Recommended Use of the Baud Rate Generator
The following is the normal sequence of operations that should occur after the
eZ80F91 is powered on to configure the Baud Rate Generator:
1. Assert and deassert RESET.
2. Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers.
3. Program the UARTx_BRG_L and UARTx_BRG_H registers.
4. Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.
BRG Control Registers
UART Baud Rate Generator Register—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by
the CPU for UART baud rate generation. The 16-bit clock divisor value is returned
by {UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two
available UART devices. Upon RESET, the 16-bit BRG divisor value resets to
. The initial 16-bit divisor value must be between
and
,
0002h
0002h
FFFFh
because the values
and
are invalid and proper operation is not guar-
0000h
0001h
anteed at these two values. As a result, the minimum BRG clock divisor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes
both bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to
1 to access this register. See Tables 94 and 95. Refer to the
UART Line Control
Register
(UARTx_LCTL) on page 196 for more information.
PS019209-0504
P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter