EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 344

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
PLL Control Register 0
The charge pump program, lock detect sensitivity, and system clock source selec-
tions can be set using this register. A brief description of each of these PLL Con-
trol Register 0 attributes is listed below, and further described in Table 207.
Charge Pump Program (CHRP_CTL).
current.
Lock Detect Sensitivity (LDS_CTL).
System Clock Source (CLK_MUX).
of the external crystal oscillator (XTAL), PLL, or Real-Time Clock crystal oscillator.
Table 207. PLL Control Register 0
(PLL_CTL0 = 005Eh)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
CHRP_CTL1
[5:4]
[3:2]
LDS_CTL1
[1:0]
CLK_MUX
Notes:
1. Bits can only be programmed when the PLL is disabled. The PLL is disabled when PLL_CTL1
2. PLL cannot be selected when disabled or out of lock.
bit 0 is equal to 0.
Value Description
00
01
10
11
00
00
01
10
11
00
01
10
11
Charge pump current = 100 µA.
Charge pump current = 500 µA.
Charge pump current = 1.0 mA.
Charge pump current = 1.5 mA.
Reserved.
Lock criteria—8 consecutive cycles of 20 ns.
Lock criteria—16 consecutive cycles of 20 ns.
Lock criteria—8 consecutive cycles of 400 ns.
Lock criteria—16 consecutive cycles of 400 ns.
System clock source is the external crystal oscillator.
System clock source is the PLL.
System clock source is the Real-Time Clock crystal oscillator.
Reserved (previous select is preserved).
R/W
P R E L I M I N A R Y
7
0
R/W
6
0
Selects the system clock source from a choice
Determines the lock criteria for the PLL.
Selects one of four values of charge pump
R
5
0
R
4
0
2
.
R/W
3
0
Product Specification
R/W
2
0
Phase-Locked Loop
eZ80F91 MCU
R/W
1
0
R/W
0
0
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