EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 290

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
EMAC Boundary Pointer Register—Low and High Bytes
The Boundary Pointer is set to the start of the Receive buffer (end of Transmit
buffer +1) in EMAC shared memory. This pointer is 24 bits and determined by
{RAM_ADDR_U, EMAC_BP_H, EMAC_BP_L}. The upper 3 bits of the
EMAC_BP_H register are hard-wired inside the eZ80F91 device to locate the
base of EMAC shared memory. The last 5 bits of the EMAC_BP_L register value
are hard-wired to keep the addressing aligned to a 32-byte boundary. See
Tables 163 and 164.
Table 163. EMAC Boundary Pointer Register—Low Byte
(EMAC_BP_L = 0044h)
Table 164. EMAC Boundary Pointer Register—High Byte
(EMAC_BP_H = 0045h)
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_L
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write.
Bit
Position
[7:0]
EMAC_BP_H
Value
00h–
FFh
Value
00h–
FFh
R/W
Description
These bits represent the Low byte of the 3-byte EMAC
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 7 of the 24-bit value. Bit 0 is bit 0 of
the 24-bit value.
Description
These bits represent the High byte of the 3-byte EMAC
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 15 of the 24-bit value. Bit 0 is bit 8 of
the 24-bit value.
P R E L I M I N A R Y
R
7
0
1
15:13
R/W
R
6
0
1
R/W
R
5
0
0
R/W
R
4
0
0
R/W
Ethernet Media Access Controller
R
3
0
0
Product Specification
12:8
R/W
R
2
0
0
eZ80F91 MCU
R/W
R
1
0
0
R/W
R
0
0
0
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