EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 261

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
uses RWP and the RRP to determine how many packet buffers remain in the Rx
buffer.
Arbiter
The arbiter controls access to EMAC memory. It prioritizes the requests for mem-
ory access between the CPU, the TxDMA, and the RxDMA. The TxDMA offers
two levels of priority: a high priority when the TxFIFO is less than half full and a
Low priority when the TxFIFO is more than half full. Similarly, the RxDMA offers
two levels of priority: a high priority when the RxFIFO is more than half full and a
Low priority when the RxFIFO is less than half full.
The arbiter determines resolution between the CPU, the RxDMA, and the TxDMA
requests to access EMAC memory. Post writing for CPU Writes results in zero-
wait-state write access timing when the CPU assumes the highest priority. CPU
Reads require a minimum of 1 wait state and can take more when the CPU does
not hold the highest priority. The CPU Read wait state is not a user-controllable
operation, because it is controlled by the arbiter. The RxDMA and TxDMA
requests are not allowed to occur back-to-back. Therefore, the maximum through-
put rate for the two Direct Memory Access (DMA) ports is 25 megabytes per sec-
ond each (one byte every 2 clocks) when the system clock is running at 50 MHz.
The rate is reduced to 20 megabytes per second for a 40 MHz system clock. The
arbiter uses the internal WAIT signal to add wait states to CPU access when
required. See Table 132.
Table 132. Arbiter Priority
TxDMA
The TxDMA module moves the next packet to be transmitted from EMAC memory
into the TxFIFO. Whenever the polling timer expires, the TxDMA reads the High
status byte from the Tx descriptor table pointed to by the Transmit Read Pointer,
TRP. Polling continues until the High status Read reaches bit 7, when the
Emac_Owns ownership semaphore, bit 15 of the descriptor table (see Table 134)
is set to 1. The TxDMA then initializes the packet length counter with the size of
Priority
Level
0
1
2
3
4
Device
Serviced
RxDMA High
TxDMA High
eZ80
RxDMA Low
TxDMA Low
®
CPU
Flags
RxFIFO > half full (FAF)
TxFIFO < half full (FAE)
RxFIFO < half full (FAE)
TxFIFO > half full (FAF)
P R E L I M I N A R Y
Ethernet Media Access Controller
Product Specification
eZ80F91 MCU
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