EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 236

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the
serial peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to
a logical 0. See Table 115.
Table 115. SPI Status Register
(SPI_SR = 00BBh)
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit
data over SPI serial bus to the slave device. A Write to the SPI_TSR register
places data directly into the shift register for transmission. A Write to this register
within an SPI device configured as a master initiates transmission of the byte of
the data loaded into the register. At the completion of transmitting a byte of data,
the SPIF status bit (SPI_SR[7]) is set to 1 in both the master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the
SPI Receive Buffer Read Only register. See Table 116.
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
Value Description
0
1
0
1
0
0
1
0000
SPI data transfer is not finished.
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit flag is cleared to 0
by a Read of the SPI_SR registers.
Reserved.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a Read of the SPI_SR register.
Reserved.
P R E L I M I N A R Y
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
Product Specification
Serial Peripheral Interface
R
2
0
eZ80F91 MCU
R
1
0
R
0
0
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