EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 267

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 135. Receive Descriptor Status (Continued)
PS019209-0504
Bit
9
8
7
6
5
4
3
2
1
0
Name
RxMcPkt
RxBcPkt
RxVLAN
RxUOpCode
RxLOOR
RxLCError
RxCodeV
RxCEvent
RxDvEvent
RxOVR
EMAC and the System Clock
Effective Ethernet throughput in any given system is dependent upon factors such
as system clock speed, network protocol overhead, application complexity, and
network traffic conditions at any given moment. The following information provides
a general guideline about the effects of system clock speed on Ethernet opera-
tion.
The eZ80F91 MCU's EMAC block performs a synchronous function that is
designed to operate over a wide range of system clock frequencies. To under-
stand its maximum data transfer capabilities at certain system operating frequen-
cies, the user must first understand the internal data bus bandwidth that is
required under ideal conditions.
For 10 BaseT Ethernet connectivity, the data rate is 10 Mbits per second, which
equates to 1.25 Mbytes per second. If the eZ80F91 MCU is operating in full duplex
mode over 10BaseT, the data rate for RX data and TX data is 1.25 Mbytes per
Description
1 = The packet contains a multicast address.
1 = The packet contains a broadcast address.
1 = The packet is a VLAN packet.
1 = An unsupported Op Code is indicated in the Op Code field of the
Ethernet packet.
1 = The Type/Length field is out of range (larger than 1518 bytes).
1 = Type/Length field is not a Type field and it does not match the
actual data byte length of the Ethernet packet. The data byte length is
the number of bytes of data in the Ethernet packet between the Type/
Length field and the FCS.
1 = A code violation is detected. The PHY asserts Rx error (RxER).
1 = A carrier event is previously seen. This event is defined as Rx
error RxER = 1, receive data valid (RxDV) = 0 and receive data (RxD)
= Eh.
1 = A receive data (RxDV) event is previously seen. Indicates that the
last Receive event is not long enough to be a valid packet.
1 = A Receive Overrun occurs in this packet. An overrun occurs when
all of the EMAC Receive buffers are in use and the Receive FIFO is
full. The hardware ignores all incoming packets until the EmacIStat
Register [Rx_Ovr] bit is cleared by the software. There is no indication
as to how many packets are ignored.
P R E L I M I N A R Y
Ethernet Media Access Controller
Product Specification
eZ80F91 MCU
248