EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 258

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
frequency at which the I
of the fastest master on the bus to ensure that START and STOP conditions are
always detected. By using two programmable clock divider stages, a high sam-
pling frequency can be ensured while allowing the MASTER mode output to be
set to a lower frequency.
Bus Clock Speed
The I
mode).
To ensure correct detection of START and STOP conditions on the bus, the I
must sample the I
fastest master on the bus. The sampling frequency should therefore be at least
1 MHz (4 MHz in FAST mode) to guarantee correct operation with other bus mas-
ters.
The I
tem clock and the value in the I2C_CCR bits 2 to 0. The bus clock speed gener-
ated by the I
clock and the values in I2C_CCR[2:0] and I2C_CCR[6:3].
I
The I2C_SRR register is a Write Only register. Writing any value to this register
performs a software reset of the I
Table 131. I
(I2C_SRR = 00CDh)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
SRR
2
C Software Reset Register
2
2
C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST
C sampling frequency is determined by the frequency of the eZ80F91 sys-
2
C Software Reset Register
2
C in MASTER mode is determined by the frequency of the input
Value Description
00h–
FFh
2
C bus at least ten times faster than the bus clock speed of the
2
C bus is sampled must be at least 10 times the frequency
W
Writing any value to this register performs a software reset of
the I
P R E L I M I N A R Y
X
7
2
C module.
W
X
6
2
C module. See Table 131.
W
X
5
W
X
4
W
X
3
Product Specification
W
X
2
I
2
C Serial I/O Interface
eZ80F91 MCU
W
X
1
2
W
X
0
C
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