EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 335

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
Table 204. Pin to Boundary Scan Cell Mapping (Continued)
PS019209-0504
Pin
CS2
CS1
CS0
A23
A23
A22
A22
A21
A21
A20
A20
A19
A19
A18
A18
A17
A17
A16
A16
A16
A15
A15
A14
A14
A13
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
3. MREQ,
shown to be associated with the least-significant bit that they control.
with D[0].
IORQ
, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
OEN
Input
Input
Input
Scan Cell #
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P R E L I M I N A R Y
Pin
PB7
PB6
PB6
PB6
PB5
PB5
PB5
PB4
PB4
PB4
PB3
PB3
PB3
PB2
PB2
PB2
PB1
PB1
PB1
PB0
PB0
PB0
PC7
PC7
PC7
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Product Specification
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
On-Chip Instrumentation
eZ80F91 MCU
Scan Cell #
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
316

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