EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 240

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
SDA Signal
SCL Signal
Transferring Data
START Condition
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The num-
ber of bytes that can be transmitted per transfer is unrestricted. Each byte must
be followed by an Acknowledge (ACK)
cant bit (msb) first. Figure 44 illustrates a receiver that holds the SCL line Low to
force the transmitter into a wait state. Data transfer then continues when the
receiver is ready for another byte of data and releases SCL.
Figure 44. I
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is
generated by the master. The transmitter releases the SDA line (High) during the
ACK clock pulse. The receiver must pull down the SDA line during the ACK clock
pulse so that it remains stable (Low) during the High period of this clock pulse.
See Figure 45.
A receiver that is addressed is obliged to generate an ACK after each byte is
received. When a slave receiver does not acknowledge the slave address (for
example, unable to receive because it is performing some real-time function), the
data line must be left High by the slave. The master then generates a STOP con-
dition to abort the transfer.
If a slave receiver acknowledges the slave address, but cannot receive any more
data bytes, the master must abort the transfer. The abort is indicated by the slave
generating the Not Acknowledge (NACK) on the first byte to follow. The slave
leaves the data line High and the master generates the STOP condition.
1. ACK is defined as a general Acknowledge bit. By contrast, the I
S
Acknowledge bit is represented as AAK, bit 2 of the I
which identifies which ACK signal to transmit. See
MSB
2
C Frame Structure
1
2
P R E L I M I N A R Y
Acknowledge from
8
Receiver
9
1
. Data is transferred with the most-signifi-
1
Table 127
Clock Line Held Low By Receiver
2
Acknowledge from
C Control Register,
Receiver
ACK
Product Specification
on page 235.
9
2
C
I
2
C Serial I/O Interface
eZ80F91 MCU
STOP Condition
P
221