EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 162

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Table 58. Timer Data Register—High Byte
(TMR0_DR_H = 0064h, TMR1_DR_H = 0069h, TMR2_DR_H = 0073h,
TMR3_DR_H = 0078h)
Timer Reload Register—Low Byte
The Timer x Reload Register—Low Byte, detailed in Table 59, stores the least-sig-
nificant byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the
timer reload value is reloaded into the timer upon end-of-count. When the reload
bit (TMRx_CTL[RLD]) is set to 1 forcing the reload function, the timer reload value
is written to the timer on the next rising edge of the clock.
This register shares its address with the corresponding timer data register.
Table 59. Timer Reload Register—Low Byte
(TMR0_RR_L = 0063h, TMR1_RR_L = 0068h, TMR2_RR_L = 0072h,
TMR3_RR_L = 0077h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMR_DR_H
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
TMR_RR_L
Value
00h–FFh These bits represent the High byte of the 2-byte timer data
Value
00h–FFh These bits represent the Low byte of the 2-byte timer
Description
value, {TMR
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.
W
P R E L I M I N A R Y
R
7
0
7
0
Description
reload value, {TMR
is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.
W
R
6
0
6
0
x
_DR_H[7:0], TMR
W
R
5
0
5
0
x
_RR_H[7:0], TMR
W
R
4
0
4
0
x
_DR_L[7:0]}. Bit 7 is bit 15
W
R
3
0
3
0
Programmable Reload Timers
Product Specification
W
R
2
0
2
0
x
_RR_L[7:0]}. Bit 7
eZ80F91 MCU
W
R
1
0
1
0
W
R
0
0
0
0
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