EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 101

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 20. Intel Bus Mode Read States—Separate Address and Data Buses
PS019209-0504
STATE T1
STATE T2
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching
of the address.
During State T2, the CPU asserts the RD signal. Depending on the instruction, either the
MREQ or IORQ signal is asserted.
Figure 11.
Intel Bus Mode—Separate Address and Data Buses
During Read operations with separate address and data buses, the Intel bus
mode employs 4 states—T1, T2, T3, and T4—as described in Table 20.
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
Intel
WR
RD
Bus Mode Signal and Pin Mapping
P R E L I M I N A R Y
Multiplexed
Bus Mode
Controller
Controller
Bus
ADDR[7:0]
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
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