MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 99
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
Freescale Semiconductor
Quantity:
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4.3.1 Read Cycle
During a read cycle, the QUICC receives data from a memory or peripheral device. If the
instruction specifies a long-word operation, the QUICC attempts to read four bytes at once.
For a word operation, the QUICC attempts to read two bytes at once. For a byte operation,
the QUICC reads one byte. The section of the data bus from which each byte is read
depends on the operand size, address signals (A1, A0), and the port size. Refer to 4.2.1
Dynamic Bus Sizing and 4.2.2 Misaligned Operands for more information.
Figure 4-15 shows a long-word read cycle flowchart and Figure 4-16 illustrates a byte read
cycle flowchart. Figure 4-17 and Figure 4-18 show functional read cycles timing diagrams
specified in terms of clock periods.
2) NEGATE AS, DS, AND OE
1) SET R/W TO READ
2) DRIVE ADDRESS ON A31–A0
3) DRIVE FUNCTION CODE ON FC3–FC0
4) DRIVE SIZE (SIZ1–SIZ0) (ONE BYTE)
5) ASSERT AS, DS, AND OE
1) LATCH DATA
5) ASSERT AS, OE AND DS
1) SET R/W TO READ
2) DRIVE ADDRESS ON A31–A0
3) DRIVE FUNCTION CODE ON FC3–FC0
4) DRIVE SIZx PINS FOR FOUR BTYES
1) LATCH DATA
2) NEGATE AS, OE AND DS
TERMINATE OUTPUT TRANSFER
START NEXT CYCLE
ADDRESS DEVICE
START NEXT CYCLE
BUS MASTER
Figure 4-15. Long-Word Read Cycle Flowchart
ADDRESS DEVICE
ACQUIRE DATA
BUS MASTER
Freescale Semiconductor, Inc.
Figure 4-16. Byte Read Cycle Flowchart
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
1) DECODE ADDRESS
2) PLACE DATA ON D31–D24, OR D23–16, OR
3) ASSERT DSACKx
1) REMOVE DATA FROM D31–D0
2) NEGATE DSACKx
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) DRIVE DSACKx SIGNALS
1) REMOVE DATA FROM D31–D0
2) NEGATE DSACKx
D15–D8, OR D7–D0.
TERMINATE CYCLE
EXTERNAL DEVICE
PRESENT DATA
TERMINATE CYCLE
PRESENT DATA
SLAVE
Bus Operation
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