MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 911

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
APPENDIX A
SERIAL PERFORMANCE
The QUICC at 25 MHz was designed to support unrestricted operation of the high-level data
link control (HDLC) or transparent protocol running on four serial communications control-
lers (SCCs) simultaneously at 2.048 Mbps. The QUICC can also support one Ethernet chan-
nel at 10 Mbps and three HDLC or transparent channels at 2.048 Mbps.
The physical clocking limit of the SCCs is higher than the sustained serial bit rate. This limit
is given as a 1:2.25 ratio between the sync clock (a clock generated in the clock synthesizer
that can be as fast as the 25-MHz system clock) and the serial clock. For example, with a
sync clock of 25 MHz, the SCCs may be clocked at 11.1 MHz. This clocking scheme allows
for high-speed bursts of data bits to be handled by the SCCs for short periods of time, sub-
ject to the FIFO sizes.
When the SCCs are connected to a time-division multiplexed channel using the time-slot
assigner present on the QUICC, the SCC physical clocking limit is a 1:2.5 ratio between the
sync clock and the serial clock. Therefore, the SCCs may be connected to a 10.0- MHz time-
division multiplexed channel with a 25-MHz QUICC. This clocking scheme allows for high-
speed bursts of data bits to be handled by the SCCs for short periods of time, subject to the
FIFO sizes.
Other devices that offer higher HDLC performance than the QUICC are the Motorola
MC68605 1984 CCITT X.25 LAPB controller and the MC68606 CCITT Q.921 multilink
LAPD controller. The MC68605 and MC68606 perform the full data-link layer protocol as
well as support various transparent modes within HDLC-framed operation at speeds of at
least 10 Mbps.
The performance figures listed in Table A-1 are for a 25-MHz system clock only.
MC68360 USER’S MANUAL
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