MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 383

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The relative priority between the two IDMAs and the SDMA channels is user programmable.
Regardless of system configuration, if the IDMA is a bus master when a higher priority
SDMA channel needs to transfer over the bus, the SDMA will steal cycles from the IDMA
with no arbitration overhead.
When the QUICC is in slave mode (CPU32+ is disabled) the SDMA can steal cycles from
the IDMA with no arbitration overhead. See Section 4 Bus Operation for diagrams of bus
arbitration by an internal master in slave mode.
7.7.2 SDMA Registers
The SDMA channels have one configuration register; otherwise, they are controlled trans-
parently to the user, through the configuration of the SCCs, SMCs, and SPI. The only user-
accessible registers associated with the SDMA are the SDMA configuration register
(SDCR), SDMA address register (SDAR), a read-only register used for diagnostics in case
of an SDMA bus error, and the SDMA status register (SDSR).
7.7.2.1 SDMA CONFIGURATION REGISTER (SDCR). The 16-bit SDCR is used to config-
ure all 14 SDMA channels. It is always readable and writable in the supervisor mode,
although writing the SDCR is not recommended unless the CP is disabled. SDCR is cleared
at reset.
Figure 7-18. SDMA Bus Arbitration (Normal Operation)
(OUTPUT)
(OUTPUT)
(OUTPUT)
NOTES:
DSACKx
(INPUT)
1. The BCLRO signal is only asserted if the SDMA bus arbitration ID is greater than
BGACK
2. The BR, BG, and BGACK signals are not affected by the SDMA bus arbitration
BCLRO
CLKO1
the BCLROID2–BCLROID0 bits in the SIM60 module configuration register.
process if the CPU32+ is enabled.
(I/O)
(I/O)
BR
BG
AS
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
SDMA INTERNALLY
REQUESTS BUS
OTHER CYCLE
S2
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
S0
NEGATED DURING
FINAL SDMA
BUS CYCLE
SDMA READ
(32 BITS)
S2
S4
S0
OTHER CYCLE
S2
S4
S0
SDMA Channels