MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 360
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 360 of 962
- Download datasheet (4Mb)
IDMA Channels
The IBPTR entry points to the next BD that the IDMA will transfer data to when it is in IDLE
state or points to the current BD during transfer processing. After a reset or when the end of
an IDMA BD table is reached, the CP initializes this pointer to the value programmed in the
IBASE entry.
ISTATE and ITEMP are for RISC use only.
7.6.4.2.2 IDMA Buffer Descriptors (BDs). Source addresses, destination addresses, and
byte counts are presented to the RISC controller using special IDMA BDs. The RISC con-
troller reads the BDs, programs the IDMA channel, and notifies the CPU32+ about the com-
pletion of a buffer transfer using the IDMA BDs. This concept is like that used for the serial
channels on the QUICC, except that the BD is larger to contain additional information.
The following bits are prepared by the user before transfer and are set by the RISC controller
after the buffer has been transferred.
V—Valid
7-36
NOTE: Entries in boldface must be initialized by the user.
OFFSET + C
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
OFFSET + 8
OFFSET + A
OFFSET + E
0 = The data buffers associated with this BD are not currently ready for transfer. The
1 = The data buffers have been prepared for transfer by the user. (Note that only one
user is free to manipulate this BD or its associated data buffer. When it is not in
auto buffer mode, the RISC controller clears this bit after the buffer has been trans-
ferred (or after an error condition is encountered).
data buffer needs to be prepared if the source/destination is a peripheral device.)
It may be only the source data buffer when the destination is a device or the desti-
nation data buffer when the source is a device. No fields of this BD may be written
by the user once this bit is set.
15
V
The only difference between auto buffer mode and buffer chain-
ing mode is that the V-bit is not cleared by the RISC controller in
the auto buffer mode. Auto buffer mode is enabled by the CM bit.
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
MC68360 USER’S MANUAL
L
Go to: www.freescale.com
10
—
DESTINATION DATA BUFFER POINTER
SOURCE DATA BUFFER POINTER
NOTE
CM
9
DATA LENGTH
—
8
—
7
—
6
—
5
—
4
—
3
SE
2
DE
1
DA
0
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