MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 248

IC MPU QUICC 25MHZ 357-PBGA

MC68360VR25VL

Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor

Specifications of MC68360VR25VL

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VL
Quantity:
310
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
System Integration Module (SIM60)
Bus Monitor
On the MC68302, this function is called the hardware watchdog.
Double Bus Fault Monitor
6-4
The SIM60 provides a bus monitor to monitor the data and size acknowledge (DSACK)
response time for all bus accesses (internal-to-internal, internal-to-external, external-to-
internal, and external-to-external). Four selectable response times allow for variations in
response speed of memory and peripherals used in the system. A bus error signal is as-
serted if the DSACK response limit is exceeded. This function can be disabled.
The double bus fault monitor causes a reset to occur if the internal HALT signal is assert-
ed by the CPU32+, indicating a double bus fault. A double bus fault results when a bus or
address error occurs during the exception processing sequence for a previous bus or ad-
dress error, a reset, or while the CPU32+ is loading information from a bus error stack
frame during an RTE instruction. This function can be disabled. See Section 4 Bus Oper-
ation for more information.
4 KB
4 KB
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 6-1. QUICC Memory Map
REGISTERS
INTERNAL
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
REGB (REGISTER BASE) = DPRBASE + 4K
DPRBASE (DUAL-PORT RAM BASE)
DUAL-PORT RAM
MBAR (SIM60)

Related parts for MC68360VR25VL