MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 744

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
On the QUICC, new functions are available in the CICR such as a choice of the CPM inter-
rupt level, a choice of the way the SCC interrupts are grouped, and a choice of the highest
priority CPM interrupt source. These functions were not available on the MC68302.
The MC68302 IPR is increased to 32 bits and is called the CIPR on the QUICC. On the
QUICC, the SIM60 can generate interrupts without using the CIPR.
The MC68302 IMR is increased to 32 bits and is called the CIMR on the QUICC.
The MC68302 ISR is increased to 32 bits and is called the CISR on the QUICC.
PARALLEL I/O PORTS
The parallel I/O pin assignment is different on the QUICC, but the three basic register types
are carried over intact. The QUICC has three I/O ports (A, B, and C); whereas, the MC68302
has two (A and B).
The PxCNT control register on the MC68302 is the PxPAR on the QUICC.
The PxDDR data direction register is the same on both devices.
The PxDAT data latch and input register is the same on both devices.
On the QUICC, some of the parallel ports have an open-drain register, PxODR, which allows
a port pin to be configured as an open-drain pin.
CHIP SELECTS
The MC68302 contains four base registers (BRx) and four option registers (ORx) to control
the chip selects. The QUICC contains a global memory register (GMR), a memory status
register (MSTAT), eight base registers (BRx), and eight option registers (ORx). The GMR
would normally be initialized first on the QUICC. Also, the QUICC chip selects contain many
enhancements over the MC68302 chip selects not discussed here.
The MC68302 BRx register most closely corresponds to the QUICC BRx.
9-24
The IV1, IV6, and IV7 bits are most closely related to the AV1, AV6, and AV7 bits of the
AVR in the SIM60.
The MOD bit does not exist on the QUICC. On the QUICC, the dedicated mode is used.
The EN bit becomes the V-bit in the QUICC BRx.
The RW bit in the BRx and the MRW bit in the ORx of the MC68302 become the WP bit
on the QUICC BRx. On the QUICC, the choice exists for asserting the chip select for
reads and writes (WP = 0) or just reads (WP = 1).
The MC68302 base address bits A23–A13 are found in BA31–BA11 of the BRx on the
QUICC. Note that the QUICC provides support for 32-bit address recognition (BA31–
BA24 are new) as well as support for smaller starting address sizes (BA12–BA11 are
new), giving the ability to begin a block on a 2K address boundary, rather than 8K on the
MC68302. To transfer a starting address from the MC68302 to the QUICC, set any bit in
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