MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 822

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

31B 5,14 DSACK¯ Asserted to Data-In, Parity-In Valid
Electrical Characteristics
10.9 BUS OPERATION AC TIMING SPECIFICATIONS (CONTINUED)
10-10
31 5,15 DSACK¯ Asserted to Data-In, Parity-In Valid
21A 11 R/W High to CS¯ Asserted
25A 13 CS¯ Negated to Data-Out, Parity-Out Invalid (Data-Out, Par-
27B 14 Data-In, Parity-In Valid to CLKO1 Low (Data Setup)
Num.
29A 4 DS , CS¯, OE Negated to Data-In High Impedance
30A 4 CLKO1 Low to Data-In High Impendance
24 12 Data-Out, Parity-Out Valid to Negating Edge of AS , CS¯,
27 15 Data-In, Parity-In to CLKO1 Low (Data Setup)
28 18 AS, DS Negated to DSACK¯ , BERR , HALT Negated
25 12 DS , CS¯, WE Negated to Data-Out, Parity-Out Invalid (Data-
23A
23B
27A
31A
39A
46A
47A
47B
29 4
30 4
35 6
22
23
26
32
33
34
37
39
46
R/W Low to DS Asserted (Write)
CLKO1 High to Data-Out, Parity-Out Valid
CLKO1 High to parity Valid
Parity Valid to CAS low
WE , (Fast Termination Write)
Out, Parity-Out Hold)
ity-Out Hold)
Data-Out, Parity-Out Valid to DS Asserted (Write)
Late BERR , HALT, BKPT Asserted to CLKO1 Low (Setup
Time)
DS , CS¯, OE Negated to Data-In, Parity-In Invalid (Data-In,
Parity-In Hold)
CLKO1 Low to Data-In, Parity-In Invalid (Fast Termination
Hold)
DSACK¯ Asserted to DSACK¯ Valid (Skew)
HALT and RESET Input Transition Time
CLKO1 High to BG Asserted
CLKO1 High to BG Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Termination Write or Read)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
Characteristic
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
t BRAGA
t DVASN
Symbol
t CNDOI
t SNDOI
t BELCL
t CHDO
t GAGN
t RWAS
t SNDN
t RACA
t RASA
t
t DVSA
t CLDH
t DADV
t CLBN
t
t CLBA
t SNDI
CHPV
t DICL
t DICL
t SHDI
t CLDI
t DADI
t DADI
t RWA
t AIHT
PVCL
t AIST
t HRrf
t GH
t GA
3.3 V/5.0 V
Min
100
25.0 MHz
30
47
10
10
35
10
20
10
10
75
10
—
—
—
—
—
—
—
—
—
—
3
1
0
0
1
1
2
1
5
Max
140
2.5
23
25
50
40
60
32
10
35
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22.5
Min
7.5
7.5
7.5
7.5
7.5
7.5
36
25
15
75
56
—
—
—
—
—
—
—
—
—
33.34MHz
3
1
0
0
1
1
2
1
4
5.0V
Max
37.5
7.5
2.5
15
15
30
45
24
26
15
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLKO1
CLKO1
CLKO1
CLKO1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns