MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 377

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

External Device Termination . If the DONEx pin is asserted externally, a transfer may be
terminated by the device even before the BCR is decremented to zero. DONEx is sampled
by the IDMA on the access to the device.
If DONEx is asserted on a bus cycle to a source device, the destination accesses will be
performed before the IDMA terminates transfers. If DONEx is asserted during a bus cycle
to a destination device, no further IDMA bus cycles occur, and the IDMA terminates trans-
fers.
The IDMA samples DONEx on the S3 falling edge of the bus cycle. Thus, the user should
assert DONEx at least one setup time before the S3 falling edge for DONEx to be recog-
nized on that bus cycle.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
When the operand transfer has terminated, STR is cleared, and a DONE bit interrupt is gen-
erated if the corresponding CMAR bit is set. The SAPR and/or DAPR are also incremented
in the normal fashion, and the BCR is decremented.
7.6.4.8.2 Auto Buffer Mode Termination. The user can suspend a transfer in auto buffer
mode by clearing the STR bit in the CMR. When STR is set once again, the transfer will con-
tinue.
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
2. The sample point at S3 assumes that the required setup time is met, as defined in Sec-
3. If SRM is cleared in the CMR (default condition), then DONEx is synchronized inter-
4. If the device is configured to be the source and dual address mode, the sample point
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
tion 10 Electrical Characteristics.
nally before it is used; therefore, DONEx must be negated one clock earlier than the
S3 falling edge to be recognized on that cycle.
used by the IDMA is S5 rather than S3. This gives the user one additional clock to as-
sert the DONEx signal.
This behavior of DONEx also applies to memory-to-memory
bus cycles, as determined by the ECO bit in the CMR.
Because DACKx timing is similar to AS timing, the user uses the
To meet the S3 sampling time, DONEx should be asserted no
later than DSACKx because the DSACKx pins are also sampled
at falling S3 to determine the end of the bus cycle.
transfers. DONEx is sampled on either the source or destination
assertion of DACKx as an indication that DONEx is asserted.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTE
IDMA Channels