MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 631

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The CPU32+ core writes the data byte into the SMC Tx BD. The SMC will transmit the data
on the monitor channel. The SMC transmitter can be programmed to work in one of two
modes:
Monitor Channel Protocol
7.11.14.1.2 SMC Monitor Channel Reception. The SMC receiver can be programmed to
work in one of two modes:
Monitor Channel Protocol
When using the monitor channel protocol, the user may issue the TRANSMIT ABORT
REQUEST command. The QUICC will then transmit an abort request on the E-bit.
7.11.14.2 SMC C/I CHANNEL HANDLING. The C/I channel (in SCIT configuration, C/I
channel 0) is used to control the layer 1 device. The layer 2 device in the TE sends com-
mands and receives indication to/from the upstream layer 1 device via C/I channel 0. In the
SCIT configuration, C/I channel 1 is used to convey real-time status information between the
layer 2 device and nonlayer 1 peripheral devices (e.g., CODECs).
7.11.14.2.1 SMC C/I Channel Transmission. The CPU32+ core writes the data byte into
the SMC C/I Tx BD. The SMC will transmit the data continuously on the C/I channel to the
physical layer device.
7.11.14.2.2 SMC C/I Channel Reception. The SMC receiver continuously monitors the C/
I channel. When a change in the data is recognized and this value is received in two suc-
cessive frames, it will be interpreted as valid data. This is referred to as the double last-look
method. The received data byte is stored by the CP in the C/I Rx BD, and a maskable inter-
rupt is generated. If the SMC is configured to support SCIT channel 1, the double last-look
method is not used.
7.11.14.3 SMC COMMANDS IN GCI MODE. The following commands are issued to the
CR.
INIT TX AND RX PARAMETERS Command. This command initializes the transmit and
receive parameters in the parameter RAM to their reset state. This command is especially
useful when switching protocols on a given serial channel.
TRANSMIT ABORT REQUEST Command. This receiver command may be issued when
the QUICC implements the monitor channel protocol. When issued, the QUICC sends an
abort request on the A-bit.
In this mode, the SMC transmits the data and handles the A and E control bits according
to the GCI monitor channel protocol. When using the monitor channel protocol, the user
may issue the TIMEOUT command to solve deadlocks in case of errors in the A and E bit
states on the data line.
In this mode, the SMC receives the data and handles the A and E control bits according
to the GCI monitor channel protocol. When a received data byte is stored by the CP in the
SMC Rx BD, a maskable interrupt is generated.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Management Controllers (SMCs)