MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 405

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

FEx—Frame Sync Edge for TDM A or B
GMx—Grant Mode for TDM A or B
TFSDx—Transmit Frame Sync Delay for TDM A or B
The L1RSYNCx and L1TSYNCx pulses are sampled with the falling/rising edge of the
channel clock according to this bit.
These two bits determine the number of clock delays between the transmit sync and the
first bit of the transmit frame. If the CRTx bit is set (recommended with IDL or GCI), then
the transmit sync is not used, and these bits are ignored.
Refer to Figure 7-29 and Figure 7-30 for an example of the use of these bits.
0 = Falling edge (Use for IDL and GCI.)
1 = Rising edge
0 = GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is in-
1 = IDL mode. A GRANT mechanism is supported if the corresponding GR1–GR4 bits
00 = No bit delay (The first bit of the frame is transmitted/received on the same clock
01 = 1 bit delay
10 = 2 bit delay
11 = 3 bit delay
L1SYNC
(FE = 1)
(CE = 0)
L1CLK
DATA
ternally supported. The grant is one bit from the receive channel. This bit is marked
by programming the channel select bits of the SI RAM with 111 to assert an internal
strobe on it. Refer to 7.8.7.2.2 SCIT Programming.
in the SIMODE register are set. The grant is a sample of the L1GRx pin while
L1TSYNCx is asserted. This GRANT mechanism implies the IDL access controls
for transmission on the D channel. Refer to 7.8.6.2 IDL Interface Programming.
as the sync.)
Figure 7-29. One Clock Delay from Sync to Data (RFSD = 01)
Freescale Semiconductor, Inc.
ONE CLOCK DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
BIT 0
For More Information On This Product,
BIT 1
MC68360 USER’S MANUAL
Go to: www.freescale.com
BIT 2
BIT 3
BIT 4
Serial Interface with Time Slot Assigner
BIT 5
END OF FRAME
BIT 0