MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 527

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

exceeds the length of the data buffer, the BISYNC controller will fetch the next BD in the
table and, if it is empty, will continue to transfer data to this BD’s associated data buffer.
When a BCS is received, it is checked and written to the data buffer. The BISYNC controller
sets the last bit, writes the message status bits into the BD, and clears the E-bit. Then it gen-
erates a maskable interrupt, indicating that a block of data has been received and is in mem-
ory. Note that the SYNCs in the non-transparent mode or DLE-SYNC pairs in the
transparent mode (i.e., an underrun condition) are not included in the BCS calculations.
7.10.20.4 BISYNC MEMORY MAP. When configured to operate in BISYNC mode, the
QUICC overlays the structure listed in Table 7-5 with the BISYNC-specific parameters
described in Table 7-9.
PRCRC and PTCRC. These value should be preset to all ones or all zeros, depending on
the BCS used.
PAREC. This 16-bit (modulo 2
the user while the channel is disabled. The counter counts parity errors on receive if the par-
ity feature of BISYNC is enabled.
NOTE: Boldfaced items should be initialized by the user.
SCC Base + 3C
SCC Base + 4C
SCC Base + 50
SCC Base + 3A
SCC Base + 3E
SCC Base + 4A
SCC Base + 4E
SCC Base + 30
SCC Base + 34
SCC Base + 38
SCC Base + 40
SCC Base + 42
SCC Base + 44
SCC Base + 46
SCC Base + 48
SCC Base + 52
The receive FIFO width (RFW) bit in the GSMR must be set for
an 8-bit receive FIFO for the BISYNC receiver.
Address
Freescale Semiconductor, Inc.
Table 7-9. BISYNC-Specific Parameters
For More Information On This Product,
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER4
CHARACTER5
CHARACTER6
CHARACTER7
CHARACTER8
16
PRCRC
PAREC
BSYNC
PTCRC
RCCM
CRCC
Name
BDLE
RES
) counter is maintained by the CP. It may be initialized by
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Long
Long
Reserved
CRC Constant Temp Value
Preset Receiver CRC16/LRC
Preset Transmitter CRC16/LRC
Receive Parity Error Counter
BISYNC SYNC Character
BISYNC DLE Character
CONTROL Character 1
CONTROL Character 2
CONTROL Character 3
CONTROL Character 4
CONTROL Character 5
CONTROL Character 6
CONTROL Character 7
CONTROL Character 8
Receive Control Character Mask
Serial Communication Controllers (SCCs)
Description