MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 673

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

W—Wrap (Final BD in Table)
I—Interrupt
L—Last
CM—Continuous Mode
F—Fault
PE—Printer Error
S—Select Error
7.13.8.11 CENTRONICS TRANSMITTER EVENT REGISTER (PIPE) . When the Centron-
ics Transmitter protocol is selected, the SMC2 event register is called the Centronics Trans-
mitter event register. It is an 8-bit register which is used to report events recognized by the
Centronics channel and generate interrupts. On recognition of an event, the Centronics con-
troller will set its corresponding bit in the Centronics event register.
The Centronics event register is a memory-mapped register that may be read at any time.
A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one
bit may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
0 = This is not the last buffer descriptor in the Tx BD Table.
1 = This is the last buffer descriptor in the Tx BD Table. After this buffer has been used,
0 = No interrupt is generated after this buffer has been serviced.
1 = The TX bit in the PIP event register will be set when this buffer has been serviced
0 = This buffer is not the last buffer of the frame.
1 = This buffer is the last buffer of the frame.
0 = Normal Operation.
1 = The R-bit is not cleared by the CP after this buffer is closed, allowing the associated
0 = The Fault status remained negated during transmission
1 = The Fault status was asserted during transmission
0 = The PError status remained negated during transmission
1 = The PError status was asserted during transmission
0 = The Select status remained asserted during transmission
1 = The Select status was negated during transmission
the CP will receive incoming data into the first BD in the table (the BD pointed to
by TBASE). The number of Tx BDs in this table is programmable, and is deter-
mined only by the wrap bit and the overall space constraints of the dual-port RAM.
by the CP, which can cause an interrupt.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R bit will be cleared if an error occurs during transmission
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Parallel Interface Port (PIP)