MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 555
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MC68360VR25VLR2
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Freescale Semiconductor
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W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Message
TC—Transmit CRC
CM—Continuous Mode
UN—Underrun
CT—CTS Lost
Data Length
Tx Data Buffer Pointer
The SCC encountered a transmitter underrun condition while transmitting the associated
data buffer.
CTS was lost during frame transmission.
The data length is the number of bytes that the CP should transmit from this BD’s data
buffer. The data length, which should be greater than zero, may be even or odd. This val-
ue is never modified by the CP.
The transmit buffer pointer, which always points to the first byte of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = When this buffer is serviced by the CP, TX, or TXE bit in the transparent event reg-
0 = The last byte in the buffer is not the last byte in the transmitted transparent frame.
1 = The last byte in the buffer is the last byte in the transmitted transparent frame. After
0 = No CRC sequence will be transmitted after this buffer.
1 = A frame check sequence as defined by the TCRC bits in the GSMR will be trans-
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable, and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
ister will be set. The TX and TXE bits can cause interrupts if they are enabled.
Data from the next transmit buffer (if ready) will be transmitted immediately follow-
ing the last byte of this buffer.
this buffer is transmitted, the transmitter will require synchronization before the
next buffer will be transmitted.
mitted after the last byte of this buffer.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
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