MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 160

• Manufacturer Part Number: MC68360VR25VL
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360VR25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5-18
ABCD
ADD, ADDI, ADDQ
ADDX
AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR, ORI,
CLR, EXT, NOT, TAS, TST
CHK
CHK2, CMP2
SUB, SUBI, SUBQ
SUBX
CMP, CMPI, CMPM
DIVS, DIVU
MULS, MULU
SBCD, NBCD
NEG
NEGX
ASL
ASL (r = 0)
LSL, ROXL
LSR (r = 0)
ROXL (r = 0)
ROL
ROL (r = 0)
ASR, LSR, ROXR
ASR, LSR (r = 0)
ROXR (r = 0)
ROR
ROR (r = 0)
Operations
Table 5-3. Condition Code Computations
Freescale Semiconductor, Inc.
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For More Information On This Product,
X
*
*
*
*
*
*
*
*
*
*
*
N
U
U
U
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
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MC68360 USER’S MANUAL
Go to: www.freescale.com
U
Z
?
?
?
?
?
?
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
U
U
U
U
V
?
?
0
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
)
C
U
?
?
?
0
?
?
?
?
0
0
?
?
?
?
0
?
0
?
?
0
?
0
?
0
0
C = Decimal Carry
Z = Z
V = Sm
C = Sm
V = Sm
C = Sm
Z = Z
Z = (R = LB) V R = UB
C =
V = Sm
C = Sm
V = Sm
C = Sm
Z = Z
V = Sm
C = Sm
V = Division Overflow
V = Multiplication Overflow
C = Decimal Borrow
Z = Z
V = Dm
C = Dm V Rm
V = Dm
C = Dm V Rm
Z = Z
V = Dm
C = Dm – r + 1
C = Dm – r + 1
C = X
C = Dm – r + 1
C = Dr – 1
C = X
(Dm – 1 V
Rm
Rm
Rm
Rm
Rm
(LB < UB)
UB < LB)
Dm
Dm
Dm
Dm
Dm
Dm V Rm
Dm V Rm
Dm V Rm
Dm V Rm
Dm V Rm
Rm
Rm
(Dm – 1 V ... V Dm – r) V Dm
Special Definition
Rm V Sm
Rm V Sm
Rm V Sm
Rm V Sm
Rm V Sm
+ Dm – r)
R0
R0
R0
R0
R0
(IR < LB) V R > UB) V
(R > UB)
Dm V Sm
Dm V Sm
Dm V Sm
Dm V Sm
Dm V Sm
?
0
Dm
Dm
Dm
Dm
Dm
(R < LB)
Rm
Rm
Rm
Rm
Rm
Rm
Rm
Rm
Rm
Rm